1. Field of the Invention
The present invention relates in general to a method of manufacturing integrated circuits and other electronic devices. In particular, the present invention relates to an improved process for photoresist patterning in the manufacture of integrated circuits and other electronic devices.
2. Description of the Related Art
With the trend toward higher integration and higher functionality of electronic devices, such as semiconductor devices, in recent years, progress continues to be made toward more intricate and multilayered wirings. In the manufacture of second generation semiconductor devices with ever higher integration and higher functionality, research has begun on using ArF excimer lasers and DUV even EUV light as exposure light sources in lithography techniques for intricate working, and progress is being made toward shorter wavelength applications. Problems raised with shorter wavelength light sources include the transmittance of the resist materials and reflection from the substrates, but surface imaging has been proposed as an effective technique to counter these problems, and a particularly effective method is the bi-layer resist method.
According to the bi-layer resist method, an organic resin is coated to a film thickness of 1-2 xcexcm, for example, to form a lower resist layer on which there is formed an upper resist layer of a thin film of about 0.1-0.2 xcexcm, and then the upper resist layer is first patterned by light exposure and development of the upper layer and the resulting upper layer pattern is used as a mask for etching of the lower layer, to form a resist pattern with a high aspect ratio. The bi-layer resist method can alleviate or prevent the influence of level differences in the substrate and reflection from the substrate surface by the lower layer resist, while the small film thickness of the upper layer resist allows improved resolution compared to single-layer resist methods. Consequently, the bi-layer resist method is more advantageous than the single-layer resist method for formation of intricate patterns on substrates with large level differences and it is therefore believed to be a more effective resist process for the shorter wavelengths of exposure light sources which will be used in the future.
U.S. Pat. No. 6,255,022 to Young et al. teach a bi-layer resist with bottom layer for planarizing and top layer containing silicon. However, a disadvantage is possible intermixing of these two resist layers. Also, as soon as the top layer is etched away, the bottom layer cannot bear high physical bombardment during etching, especially for noble metals used in FeRAM.
U.S. Pat. No. 5,922,516 to Yu et al. teach a bi-layer resist with bottom layer for planarizing and top layer subjecting to silylation. However, this method also has the disadvantages mentioned above.
An object of the present invention is to provide a bi-layer resist process to prevent the two resist layers from intermixing.
Another object of the present invention is to provide a bi-layer resist process, wherein the resist layer can withstand high physical bombardment during etching.
In accordance with the objects of this invention a new bi-layer resist process for semiconductor processing is achieved. A layer to be etched is provided on a substrate. The layer to be etched is coated with a bottom silicon-containing resist layer. The bottom silicon-containing resist layer is baked. The bottom silicon-containing resist layer is treated to form a silicon oxide layer on a surface of the bottom silicon-containing resist layer. The silicon oxide layer is coated with a top resist layer. The top resist layer is baked. The top resist layer is exposed to light and developed to form a pattern in the top resist layer. The pattern is transferred through the silicon oxide layer to the bottom resist layer.